The invention relates to field effect transistors, FETs, particularly those capable of operation at microwave and millimeter wave frequencies.
Electrical performance of a semiconductor device is dependent upon structural configuration and the ability of the structure to reduce elemental parasitics such as series resistance, shunt capacitance and series inductance. Reliability is dependent upon the metallurgical techniques used to provide the junction passivation and to produce ohmic and schottky contacts.
Although the last decade has seen substantial progress in the development and fabrication of FET devices that provide excellent performance and reliability, there remains a need for further development in devices intended for application in the millimeter wave frequency range.
FIG. 1 shows known conventional FET structure fabricated on semi-insulating or dielectric substrate 1 and active epitaxial N layer 2. Such substrates are typically made of gallium arsenide Gate 3 controls spreading of depletion region 4 which in turn controls conduction between source 5 and drain 6 by pinching off or opening channel 7. Dimension 8 is the source to gate length Lsg. Dimension 9 is the gate length Lg. Dimension 10 is the gate to drain length Lgd. Ohmic contacts are made by sinter alloying a metallic film composed of nickel-germanium gold to the active layer 2. The nickel-germanium gold usually ranges between 500 and 1,000 angstroms in thickness, and is typically composed of 12 percent germanium or nickel germanium and 88 percent gold. Using this contact composition, a contact resistivity ranging from 3 to 5.times.10.sup.-6 ohms cm.sup.-3 can be achieved. The input series resistance can be in the 3 to 5 ohm range if the concentration of active N layer 102 ranges from 1 to 3.times.10.sup.17 cm.sup.-3, and the source ohmic contact is positioned within 1 mircon of the gate edge.
For the configuration in FIG. 1, the minimum input source series resistance that can be achieved is limited by the finite source to gate length Lsg of the conducting channel. For some low noise and low power applications, this channel length has been reduced to 0.5 microns. However, the reliability and yield of such devices is poor since gold and nickel can easily interdiffuse with gallium arsenide and eventually diffuse into the active conducting channel, resulting in performance degradation and ultimately catastrophic failure. An additional limitation of the structure is the effective length of the channel under the gate which is much greater than the metallurgical gate length, resulting in greater effective source to gate capacitance and consequently a lower maximum frequency of oscillation. Furthermore, the conducting channel is fully exposed to ambient and to contaminants that contribute to poor RF performance and reliability.
To improve reliability, various dielectric layers, such as silicon dioxide SiO.sub.2 and silicon nitride Si.sub.3 N.sub.4 have been used to passivate the exposed conducting channel. SiO.sub.2 is known to be ineffective as a passivation for sodium ions, the most notably troublesome contaminant. On the other hand, Si.sub.3 N.sub.4 is an effective passivation only for sodium ions. In order to provide a complete passivation, both SiO.sub.2 and Si.sub.3 N.sub.4 must be used. For conventional FETs, the use of these dielectrics often increases the parasitic capacitance between the source and gate Csg, between gate and drain Cgd, and between source and drain Csd. These added parasitic capacitances effectively limit the efficient operation of conventional FETs to well below 20 GHz.
FIG. 2 shows another known FET configuration, developed to improve the performance of the structure of FIG. 1. N+ expitaxial layers 11 and 12 are provided beneath source and drain contacts 13 and 14 on N layer 5 on semi-insulating or dielectric substrate 16. Gate 7 controls spreading of depletion region 18 to control conduction through channel 19. In the known configuration of FIG. 3 gate 20 is recessed in N layer 21, with the remaining structure being comparable to FIG. 2 with substrate 22, N+ epitaxial layers 23 and 24, source and drain contacts 25 and 26, depletion region 27 and channel 28. The quality of the epitaxial layers 11, 12 and 23, 24 in FIGS. 2 and 3 is difficult to evaluate. In addition, the fabrication steps are more complex and result in poor device yield and uniformity.
The structures of FIGS. 2 and 3 do, however, offer advantages over the structure of FIG. 1, including the ability to achieve lower contact series resistance, lower channel resistance and higher voltage breakdown. The lower contact resistance is achieved by using a highly doped N+ layer with a doping concentration of approximately 2.times.10.sup.18 cm.sup.-3. The lower channel resistance is achieved by using a thicker active N layer outside the gate region where a recessed gate is employed as shown in FIG. 3. A higher voltage breakdown is achieved by providing a greater separation between the gate and drain. In addition, the N+ layer can be extended close to the gate to further reduce the parasitic series resistance of the source and drain.
Although some improvement in electrical performance is attained by the structures shown in FIGS. 2 and 3, the degree of such improvement is still not adequate. Furthermore, there is no appreciable improvement in reliability over the structure of FIG. 1. The structures of FIGS. 2 and 3 are similar to that of FIG. 1 in that the channel is exposed to ambient and contaminants, the ohmic contact to the source is still within 1 micron of the gate, and the effective gate length is greater than the metallurgical length of the gate.
FIG. 4 shows another known FET structure, developed for low power, high speed logic applications. This device is similar to that of FIG. 1 except that there is a first N+ layer 29 under source 30 and a second N+ layer 31 under drain 32. The remaining structure is comparable, with substrate 33, N layer 34, gate 35, depletion region 36 and channel 37. N+ layers 29 and 31 in FIG. 4 differ from N+ layers 11, 12 and 23, 24 in FIGS. 2 and 3 in that layers 29 and 30 extend up to the gate region rather than being confined to the areas immediately below the source and drain. Layers 29 and 31 occupy the area which is occupied by the N layer 15 in FIG. 2 and 21 in FIG. 3 except for the small segment lying directly below gate 35. For low power, high speed logic devices, the required voltage breakdown at 10 microamps is typically in the 3 to 5 volt range. The structure of FIG. 4 makes use of ion implantation to implant the N+ layers into semi-insulating or dielectric substrate 33. To achieve low series resistance, the gate is formed prior to the ion implantation and acts as a mask during the processs. The vertical facing edges 38 and 39 of N+ layers 29 and 31 are colinear with the edge of gate 35, thereby providing the desired lower series resistance. Ohmic contacts of nickel germanium gold are then formed on the implanted N+ layers at 30 and 32.
Although the series resistance of the device of FIG. 4 is reduced as compared to the devices of FIGS. 1-3, voltage breakdown and reliability are also reduced. The voltage breakdown that can be achieved depends upon the carrier concentration of the N+ layers and upon the separation between the edges of the N+ layers and the gate. If the N+ layers are doped with a concentration of 10.sup.19 cm.sup.-3, the expected voltage breakdown at 10 microamps is well below 1 volt, making the device unreliable and difficult to fabricate. Another factor detracting from reliabilty of the device of FIG. 4 is that it must be annealed at about 900.degree. C. following the ion implantation process. At this temperature, the gate metal tends to interdiffuse with the N+ layer about its edges, to form an ohmic contact or a short circuit.
FIG. 5 shows another known FET configuration, generally referred to as a permeable base transistor PBT, and is a normally OFF device developed to extend the operating frequency range of FETs into the millimeter region. The device includes an N+ layer 40, an N layer 41, a source 42, a gate 43, a drain 44 and depletion regions 45. FIG. 5 shows a cross sectional view with gate 43 extending centrally through N layer 41 and divided into a series of fingers such as 46 between which are the depletion layers 45. The carrier doping concentration of N layer 41 is about 1.times.10.sup.16 cm.sup.-3 in order to fully deplete the regions 45 between adjacent gate fingers at zero bias. Dimension 47 is less than the width of the depletion region pair at zero bias. Dimension 48, the thickness of the gate finger, can be less than 500 angstroms. For a doping concentration in the N layer of 1.times.10.sup.16 cm.sup.-3, a dimension 47 of about 2,000 angstroms, a distance from the gate to the drain, dimension 49, of 0.6 microns, a distance from the gate to source, dimension 50, of 0.4 microns, and a gate length Lg, dimension 48, of 200 angstroms, the calculated power delay product is nearly 1.times.10.sup.-15 joules, the maximum unity gain frequency is in excess of 200 gigahertz, and the minimum frequency of oscillation is nearly 1,000 gigahertz.
Fabrication of the structure of FIG. 5 is extremely difficult. In particular, it requires the growth of a single crystal epitaxial layer at the edges and over the amorphous metal fingers of the gate. To achieve short gate lengths, the gate metal must be made very thin, increasing the gate resistance to an intolerably high value. To achieve a fully depleted layer, the value of the carrier concentration is reduced by an order of magnitude from 1.times.10.sup.17 cm.sup.-3 for a conventional FET to 1.times.10.sup.16 cm.sup.-3, producing an increase in the resistivity of the epilayer. Although the PBT structure of FIG. 5 has been fabricated, the experimental results to date have not been encouraging. The best performance obtained with these devices thus far only approaches that achieved with conventional devices at frequencies well below 20 gigahertz.
The goal in the development of the above conventional and PBT FET structures was to increase the maximum oscillating frequency, lower the noise figures where the application was low noise amplifiers, increase the power output where the application was power amplifiers, and increase the switching speed where the application was gigabit logic circuitry. The predicted maximum frequency of oscillation for conventional devices is 120 to 140 gigahertz. This limitation is attributed to the finite parasitic series resistance of the N layer beneath the source, and the length of the depletion layer beneath the gate, which is larger than the physical length of the gate material. This makes the effective gate capacitance greater than that calculated from the physical dimensions of the gate and accordingly limits the operation of the device to lower frequencies.
FIG. 6 is a schematic perspective cut-away view of conventional FET structure, and FIG. 7 shows the equivalent electrical circuit. The device includes a semi-insulating dielectric substrate 51, N layer 52, source 53, gate 54 and drain 55. The corresponding equivalent electrical circuit includes gate resistance Rg 56, source resistance Rs 57, intrinsic channel resistance Ri 58, drain to source resistance Rds 59, drain resistance Rd 60, source to gate capacitance Csg 61, gate to drain capacitance Cgd 62, source to drain capacitance Csd 63, and a current generator eg-gm 64 which produces a current equal to the gate voltage eg multipled by the transconductance gm. For the circuit of FIGS. 6 and 7, the maximum frequency of oscillation fm is given by: ##EQU1## where the frequency at unity gain f.sub.T is given by ##EQU2## and gm is the transconductance ##EQU3## and EQU T.sub.3 =2.pi.RgC.sub.dg
As indicated in the above equations, to achieve a high maximum frequency of oscillation, it is necessary to maximize f.sub.T. This is realized by decreasing the gate to source capacitance Cgs, the gate to drain capacitance Cgd, the parasitic source resistance Rs, the gate resistance Rg, the intrinsic channel resistance Ri, and by increasing the transconductance gm.
The value of Rs generally cannot be reduced below 1 ohm when using conventional FET structures designed for use in low noise or power application. Rs and Ri can be somewhat reduced by increasing the carrier concentration in the active N layer. However, this results in the gate to drain voltage breakdown also being reduced.